The table below shows the hardware timers of the Colibri T20 and how they are mapped to operating system functions:
| Timer | Windows CE usage | Notes |
|---|---|---|
| TMR1 | Watchdog | Required only if Windows CE watchdog is enabled |
| TMR2 | AVP | Required for multimedia playback |
| TMRUS | Interrupts are not possible | |
| TMR3 | Profiling | Required for special debug scenarios only |
| TMR4 | System Tick | Always occupied by Windows CE |
The timer interrupts were reserved in Windows CE6/7 V1.0 and earlier, so it was not possible to register an interrupt on any of these timer events.
Later versions allow the use of TMR1 and TMR3, if the customer does not enable the related default functionality. Toradex recommends to use TMR3 for customer specific timer interrupts.
In addition, each of the two CPU cores have a built-in private and global timer, which are not used by the system. Here's a link to ARM's documentation. See section Global timer, private timers, and watchdog registers.
| Timer | CPU core | Notes |
|---|---|---|
| Private Timer | Core 1 | Independent countdown timer |
| Global Timer | Core 1 | Common free-running counter between cores, separate control registers for each CPU core |
| Private Timer | Core 2 | Independent countdown timer |
| Global Timer | Core 2 | Common free-running counter between cores, separate control registers for each CPU core |
There are several limitations if you want to use these timers:
The timers are clocked at 1/4 of the current CPU speed. So if dynamic frequency switching is enabled, the counter frequency changes accordingly.
Windows CE only allows interrupts on CPU core 1. So only the timers on core 1 can be used in interrupt mode. Information about the interrupt numbers can be found here.
Timers on core 1 use the same register address map as timers on core 2. If the code is executed on core 1, the timer on core 1 is accessed, and if the code is executed on core 2, the timer on core 2 is accessed.
