Apalis Module Architecture

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Introduction

Overview

This document is a specification which defines the Apalis Computer-on-Module (referred to hereafter as “module”). It defines the interfaces in terms of functional and electrical characteristics, signal definitions and pin assignments. It also defines the mechanical form factor, including key dimensions.

A PDF version of this document can be downloaded using the link below.

• Apalis Module Specification

A whitepaper on the Apalis Module Standard is a available below

• Apalis Module Standard Whitepaper

Motivations

The following motivations are central to the definition of the new Apalis module specification. It should be clearly noted that the Apalis computer module family is not a replacement for the Colibri computer module family. Both are very complementary to one another, and whilst may overlap in terms of suitability for some specific applications, they differ significantly in a variety of areas including, but not limited to, size, features and cost.

1. As ARM based SoC (System-on-Chip) technology continues to evolve, support for a wider range of interfaces is being added, such as PCI-express, Gigabit Ethernet, HDMI, etc. The Apalis module will enable customers to benefit from these evolutions. It should also be noted that nothing in the module specification restricts any Apalis based products from using non-ARM architectures. In this respect, the specification is very architecture independent.

2. With the recent advancements in ARM based SoC technology, including but not limited to the addition of a wider variety of high speed interfaces and the huge advancement in graphics capability, such as 2D/3D hardware acceleration, full HD rendering and multiple display support, it is possible to access markets previously reserved for higher power, x86 based technologies, such as the Intel Atom. The Apalis module will provide a platform with which to enable this technology to compete in these application areas and address the shortcomings of existing x86 based products.

3. As the pace in performance advancement is accelerating faster than the increase in performance efficiency, we are seeing an increasing trend in power consumption in high performance ARM based SoCs. Whilst passive cooling is still perfectly viable in many applications, this increase in power consumption means that allowances for additional cooling solutions, such as heat spreaders for conduction cooling, must be made. The Apalis module provides a robust, rigid mounting mechanism to support such thermal solutions.

4. The Apalis module has been developed from in depth research into different technologies, rather than a specific SoC. This will help to future proof the Apalis module architecture whilst making it suitable for supporting a wide range of SoCs.

5. The Apalis module encapsulates the complexity associated with modern day electronic design, such as high speed impedance controlled layouts with high component density utilising blind and buried via technology. This allows the customer to create a carrier board which implements the application specific electronics which is generally much less complicated. The Apalis module takes this one step further and implements an interface pin out which allows direct connection of real world I/O ports without needing to cross traces or traverse layers, referred to as Direct Breakout™. This becomes increasingly important for customers as more interfaces move toward high speed, serial technologies that use impedance controlled differential pairs, as it allows them to easily route such interfaces to common connectors in a simple, robust fashion.

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Module Overview

Architecture

The block diagram below shows the basic architecture of the Apalis module, depicting the standard interfaces and some examples of type specific interfaces.

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Features

Features of the Apalis module are split into two distinct groups; standard and type specific.

Standard features are features that are allocated for use on every Apalis module. Although they may not be fully supported or implemented on every module, pins are reserved specifically for them and shall not be used for any other purpose in the future. This guarantees electrical compatibility between designs which only make use of standard features, helping to ensure carrier board design longevity and support for future module designs.

A type specific feature is a feature which is not guaranteed to be functionality or electrically compatible between modules. If a carrier board design uses such features, then it is possible that other modules in the Apalis module family do not provide these features and instead provide other features on the associated pins. In this case, Apalis modules which are suitable for use in the carrier board design may be restricted.

Interface Summary

This section provides a list of interfaces that are defined as standard, and some examples of those interfaces which may be type specific.

Standard Interfaces

By dedicating specific pins for specific functions, the Apalis module family is able to ensure electrical and functional compatibility between module family members, helping future proof designs against advances in technology and providing an upgrade path for products, decoupling the product from reliance on a specific device or device family. Every effort shall be taken to maintain functional compatibility between module family members where it commercially and technically viable.

The table below shows the standard interfaces that are provided by an Apalis module. The “GPIO Capable” column indicates whether, for a specific interface, the assigned pins can be used as GPIOs. Yes and No are self-explanatory, Optional indicates that it may be possible for some modules, but not all. The “Standard” column indicates the number of interfaces that the specification allows for in the standard pin out. Customers should consult the datasheet for specific Apalis module variants to check which interfaces are available for that module.

Type Specific Interfaces

Type specific interfaces allow for the possibility of including interfaces which may not yet exist or be widely adopted, or interfaces which may be specific to a particular device or groups of devices. They also offer a mechanism of extending features which are present on the standard interfaces, such as providing additional PCI-Express lanes. This provides the Apalis module with the flexibility of being able to reconfigure a subset of pins for different uses between different modules.

It should be noted that type specific interfaces will be kept common across modules that share such interfaces where possible. For example, if both module A and module B have three additional PCI-Express lanes which are available in the same configurations as a type specific interface, then they shall be assigned to the same pins in the type specific area of the connector. Hence, both module A and module B shall share compatibility between these parts of the type specific interface.

Interfaces: Apalis T30

The table below shows the interfaces that are supported on the Apalis T30 module, and whether an interface is provided on standard or type specific pins. The PCI-Express interface is an example of an interface that makes use of standard and type specific pins – 1 lane is provided as part of the standard interface pin out and the additional 4 lanes are type specific.

Interfaces: Apalis iMX6

The table below shows the interfaces that are supported on the Apalis iMX6 module, and whether an interface is provided on standard or type specific pins. On Apalis iMX6, the type specific provides interface like MIPI-CSI-2, MIPI-DSI, Media Local Bus, USB, GPIOs and few control signals.

Module and Carrier Board Compatibility

To ensure any carrier board design is 100% compatible with all Apalis modules, only the standard interfaces should be used.

If a custom carrier board design uses any type-specific interfaces, then it may not be 100% compatible with all Apalis modules. Where type specific interfaces are common between different Apalis modules, they shall be provided on the same pins where possible. Therefore, designs that make use of the type specific interfaces of a specific Apalis module may be compatible with other Apalis modules – please check the interface specifications of individual Apalis modules carefully.

Connector

The Apalis module is based around the MXM3 (Mobile PCI-Express Module) edge connector. This connector has been adopted by various manufacturers for use in the embedded CoM market and, based on the range of connectors available on the market at the current time, is the only suitable connector based on the Apalis module requirements.

A picture of the MXM3 connection can be found below.

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The connector provides a total of 310 usable contacts. A large proportion of the contacts are reserved for the standard interfaces, whilst a smaller subset is reserved for type specific interfaces.

The recommended connector for the Apalis module is the JAE MM70-314-310B1, which has a board height of 3.0mm.

MXM SnapLock™

The Apalis module can be fixed easily to the carrier board using either M3 screws or a unique connector mechanism called MXM SnapLock™. MXM SnapLock™ uses an edge retention connector which is mounted on the carrier board and retains the Apalis module in place using two metal retaining clips and locating pips. For many applications and during development, this provides a simple retention mechanism.

For applications where the system is likely to experience a high level of vibration or harshness, a set of M3 bolts combined with SMT aluminium stand-offs mounted in the carrier board can be used.

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Interface Specifications

Signal Naming Convention

Where there are multiple signals of the same type which are part of a group and are identified by a suffix index (e.g. PWM1, PWM2, etc.), then the index always starts with a one (as opposed to a zero). For signals which are named after a standard or follow a widely acknowledged common naming convention (such as the Ethernet or LVDS interfaces), they may use a zero based index.

Differential pair signal components are suffixed with either a “+” or “-“. Active low signals are suffixed with a “#”. The underscore (“_”) is used as a separator to split component parts of the signal name (such as signal group, channel and signal descriptor components) to make the signal name easy to read and interpret.

Signal Definition

This section contains detailed information on the signals provided by the Apalis module, such as signal class and voltage domains. Please refer to the key in figure 5 for the various voltage domain definitions.

Only those voltage domains marked in green are required to be supplied externally for module operation, and those in orange are optional. The domains that are not marked in green or orange are not required to be supplied to the module.

Some of the voltage domains specified are used purely to indicate power supply tolerances on pins which are specified to operate on that domain. Hence, they are not necessarily power supplies that are generated by the module nor required by the module.

Check carefully in individual signal definitions to determine the voltage domain to which a signal belongs. Do not assume that a signal which shares a group or class name with a voltage domain is automatically on that voltage domain. For instance, the VCC_HDMI voltage domain is applicable for supply voltage and control signals, but not for the differential mode signals.

JTAG and Generic Test Point Interfaces

Every Apalis module provides a series of 20 test points; 10 along the left side and 10 along the right side of the bottom of the module PCB.

Each set of test points is symmetrical about the centered Y-axis (the Y plane is orthogonal to the connector edge). These test points shall provide access to any JTAG interface that is supported by the module (this is normally the JTAG interface as provided by the SoC) as well as module specific signals, generally for the purposes of measurement.

The JTAG interface pins are always the topmost 7 pins on the left edge of the module when the module is viewed from the top side. These test points are always reserved for the JTAG interface and will never provide any other signals. They are depicted by green primitives in figure 7. The remaining 13 test points are module specific pins. The signals connected to these test points are defined in the datasheet for each individual Apalis module. They are depicted by orange primitives in figure 7.

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Parallel LCD

The parallel LCD interface is a 24 bit interface. The signals are defined in groups of pins assigned to the Red, Green and Blue, with R7, G7 and B7 being the Most Significant Bits (MSBs) and R0, G0 and B0 being the Least Significant Bits (LSBs) for the respective colours. To ensure compatibility between modules, the display interface should always be used in 24 bit mode.

To use displays which require fewer bits (e.g. 18 or 16 bit displays), simply do not connect the bottom n LSBs for each colour, where n is the number of signals that are not required for a specific colour. For instance, to connect an 18 bit display, R0, R1, G0, G1, B0 and B1 will remain unused, and R2, G2 and B2 become the LSBs for this configuration. More detailed information regarding configuration shall be provided in the reference design guide.

Parallel Camera

For compatibility between modules, the parallel camera interface shall normally be configured by default to operate in 8 bit YUV mode. Modules may support other modes with greater bit depths; in such cases, additional pins will be made available as type specific interfaces as necessary, and compatibility between different modules for such modes cannot be guaranteed.

Physical Pin Definition and Location

Signal definitions in terms of physical pins and their locations on the Apalis module can be found in the appendix. The table in appendix C defines the physical pins and their location on the Apalis module. This definition also includes missing pins (marked with a grey cell) to represent the physical space on the connector where these pins are missing.

The total number of usable pins on the module is 310. The ground pin count is 41 (~13%). The main power supply (VCC) power pin count is 10.

Direct Breakout™

Direct Breakout™ aims to reduce complexity of carrier board routing from the module connector to the real world I/O ports by making it possible to route signals without requiring any trace gathering or cross over for critical signals. This is achieved by taking care of the complexity of routing high speed, impedance critical signals from the source IC to the edge connector on the Apalis module. I/O is generally gathered into functional “rooms” on the connector so that all signals associated with a specific interface are in one place, reducing routing complexity.

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The above image shows the concept of direct breakout by illustrating how complex routing and layout is encapsulated on the Apalis module, providing the potential for simple routing on the carrier board.

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Mechanical Specifications

Overview

The Apalis module form factor mechanical dimensions have been specified based on careful analysis of required board space for typical device packages (e.g. 23mm x 23mm 0.8mm pitch SoC, 4 x16 memory ICs, power ICs and peripheral ICs) and certain key features (e.g. as dual channel [2 x 32bit] memory bus). This has been balanced with the requirement to keep the form factor as small as is reasonably possible. A single mechanical size has been defined.

Mounting and Fixation

MXM SnapLock™ or M3 screws in combination with threaded standoffs shall be used to fasten the module to the carrier board. A keep out area on the bottom side of the module located in the centre is reserved to allow a mechanical standoff on the carrier board to come into contact with the PCB when the module is fully inserted. This will allow pressure to be placed on the top side of the module which may be required for thermal cooling solutions without exerting a bending moment on the PCB. Carrier board design requirements shall be detailed in a separate carrier board design guide application note.

Module Size

Width, Length, Height and Key Primitives

The below image shows a mechanical drawing of the outline of the Apalis module together with key dimensions.

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The Apalis module extends in the Y plane (the plane which is orthogonal to the connector edge) for 45mm from one PCB edge to the other. The thickness of the Apalis module PCB is 1.2mm.

Pin Numbering

The diagrams in figures 10 and 11 show the pin numbering schema on both sides of the module. The schema deviates from the unrelated MXM3 standard pin numbering schema. Pins on the top side of the module have an even number and pins on the bottom side have an odd number.

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The pin number increases linearly as a multiple of the pitch – that is, pins which are not assembled in the connector (between pins 18 and 23) are also accounted for in the numbering (pins 19 through 22 do not exist). Similarly, pins which do not exist due to the connector notch are also accounted for (pins 166 through 172).

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Electrical Specifications

Power Supplies

All Apalis modules are capable of being powered with a single main power supply powering VCC and AVCC, and if required, a low current backup power supply for purposes such as Real Time Clock (RTC) support. To minimise the impact of noise on the sensitive analogue parts of the system, it is highly recommended that VCC and AVCC be supplied through independent power supplies (for instance, AVCC can be generated via an LDO due to its low current requirements). Based on the power supply rating of the connector pins and the number of pins assigned as main (VCC) power supply pins, the maximum current draw from VCC is 5 amps.

Further carrier board power supply requirements in terms of power rating, isolation and decoupling, bulk capacitance and characteristics such as ramp up rate, etc. will be detailed in a separate carrier board design guide application note.

Power Control

There are no power control features built into the module from the power on/power off perspective. If a specific implementation requires a power on button, then it shall be the responsibility of the carrier board to implement this functionality.

VCC and AVCC are the two minimum power supplies which are required to be present for the module to become operational. Once VCC is present and is within specification, then the module will power up and start normal operation automatically.

VCC_BACKUP is not required for the module to start normal operation, however, it is permanently required if the application requires features which rely on this supply being always on, such as the Real-Time Clock (RTC).

Back Feed Protection

Protection from back feeding from devices on the carrier board can be achieved using the signal “POWER_ENABLE_MOCI”. This signal will be asserted by the module to indicate that the carrier board can power up any external devices (such as signal transceivers, converters, level shifters, secondary MPUs, etc.) which may otherwise cause undesired back feeding prior to and during the module power up process. Detailed information on the use of this signal shall be provided in a separate carrier board design guide application note.

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Appendix A – Module Top Side Signal Definition

Appendix B – Module Bottom Side Signal Definition

Appendix C – Physical Pin Definition and Location

Disclaimer:

Copyright © Toradex AG. All rights reserved. All data is for information purposes only and not guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Brand and product names are trademarks or registered trademarks of their respective owners. Specifications are subject to change without notice.