HAR-11275 | Known Issue | Possible Noise on Audio Output during Reset Cycle | Apalis iMX6D V1.0 WinEC Apalis iMX6D V1.1 WinEC Apalis iMX6Q V1.0 WinEC Apalis iMX6Q V1.1 WinEC | |
Description: The audio codec on the SGTL5000 on the module does not feature a dedicated reset input. If a sound is playing back during a reset cycle, the SGTL5000 remains in playback mode. The audio codec is then repeating the last short sample, which remains in its buffer. This creates an audible noise at the output. The actual noise depends on the sample which is in the buffer. This noise is retained until the audio codec is reinitialized during the booting process.
The issue only appears if the reset is initiated by the RESET_MICO# reset (e.g., pressing the reset button on the evaluation board). The effect has not been seen during software-initiated reset cycles or regular power cycles. Workaround: There is currently no workaround available. Try to avoid pressing the reset button while any sound is played back from the on-module audio codec. |
HAR-11272 | Known Issue | Secure Boot Vulnerabilities (NXP ERR010872 and ERR010873) | Apalis iMX6D 512MB V1.1B WinEC Apalis iMX6D 1GB IT V1.1B WinEC Apalis iMX6Q 1GB V1.1B WinEC Apalis iMX6Q 2GB IT V1.1C WinEC | |
Description: These errata are actually NXP errata affecting all i.MX and Vybrid processors. There are two issues in the boot ROM when using the processors in a security-enabled configuration (SEC_CONFIG[1] eFUSE is programmed). By default, this fuse is not programmed on Toradex modules. Customers not fusing this setting are therefore not affected by these issues.
Customers using the security-enabled configuration are affected by these issues. More information can be found in the respective NXP errata documents:
https://docs.toradex.cn/104705-err010872-secure-boot-vulnerability-erratum-preliminary-rev0.pdf
https://docs.toradex.cn/104706-err010873-secure-boot-vulnerability-erratum-preliminary-rev0.pdf Workaround: Please refer to the documents mentioned above for workarounds. |
HAR-9468 | Known Issue | SkyHigh eMMC's not properly initialized when booted from other media in pSLC mode Apalis iMX6 | Apalis iMX6D 512MB V1.1C WinEC Apalis iMX6Q 1GB V1.1C WinEC Apalis iMX6Q 1GB V1.1D WinEC Apalis iMX6Q 1GB V1.1Y WinEC Apalis iMX6D 512MB V1.1A Apalis iMX6Q 1GB V1.1A | Apalis iMX6D 512MB V1.1C WinEC Apalis iMX6Q 1GB V1.1D WinEC Apalis iMX6Q 1GB V1.1Y WinEC Apalis iMX6D 512MB V1.1A Apalis iMX6Q 1GB V1.1A |
Customer Impact: When configuring and using the SkyHigh eMMC in MLC mode customers are not affected. Customers using pSLC (pseudo-SLC) mode and trying to boot from SD card the module may not work. Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and trying to boot from SD card the module may not work. Workaround: There are three possible workarounds:
1) Access the eMMC from U-Boot before launching the Kernel by using the following command: ls mmc 0.4:0 /boot
2) Update the eMMC firmware according to the instructions:
https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc
3) Modules produced after 09.12.2022 are not affected |
HAR-9450 | Known Issue | STMPE811 ADC can get wrongly strapped if voltage is applied to ADC_AD1 input during boot | Apalis iMX6 V1.0 Apalis iMX6 V1.1 | Not applicable |
Customer Impact: If voltage is applied to ADC_AD1 input during boot, the ADC inputs and the touch interface may not work as the STMPE811 is not accessible on the I2C bus. Description: The STMPE811 ADC and touch controller IC uses the IN0_GPIO1 pin for strapping between I2C and SPI mode. If the pin is high during the power-up of the controller, the chip gets misconfigured as an SPI device. In this case, the chip cannot be accessed over the I2C mode and is unavailable.
The IN0_GPIO1 is used as ADC_AD1 input of the module (edge connector pin 307). A voltage applied to the analog input ADC_AD1 during the module's power-up can cause the ADC and touch controller to be strapped wrongly and therefore not accessible.
The module features a circuit that pulls down the ADC_AD1 input during the reset state to prevent false strappings. However, this circuit may not work correctly if there is extensive backfeeding to the module. The best prevention is not applying any voltage to the ADC_AD1 input while the module is not powered. Workaround: Ensure that there is no voltage applied to the ADC_AD1 input until the module booted. Use any of the other ADC inputs instead. |
HAR-9439 | Known Issue | Endurance degradation of Apalis iMX6 modules with the SkyHigh eMMC in pSLC mode | Apalis iMX6D 512MB V1.1C WinEC Apalis iMX6Q 1GB V1.1C WinEC Apalis iMX6Q 1GB V1.1D WinEC Apalis iMX6Q 1GB V1.1Y WinEC Apalis iMX6D 512MB V1.1A Apalis iMX6Q 1GB V1.1A | Apalis iMX6D 512MB V1.1C WinEC Apalis iMX6Q 1GB V1.1D WinEC Apalis iMX6Q 1GB V1.1Y WinEC Apalis iMX6D 512MB V1.1A Apalis iMX6Q 1GB V1.1A |
Customer Impact: Using the SkyHigh eMMC based module in pSLC (pseudo-SLC) mode and writing more than 32TB to the eMMC, will lock up the device, not allowing any further writes to the eMMC. Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and writing more than 32TB to the eMMC, the eMMC firmware will lock up the device, not allowing any further writes to the eMMC. The theoretical lifetime data write capacity for SkyHigh eMMCs in pSLC mode would be 60TB. By default, Toradex doesn't enable the pSLC mode and therefore doesn't run into this problem. Workaround: SkyHigh implemented an FW fix. Customers using pSLC mode and writing more than 32TB during the lifetime of the product can execute a single-step FW update: https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc
Products produced after 09.12.2022 are not affected |
HAR-8210 | Known Issue | POWER_ENABLE_MOCI indeterminate due to backfeeding on Apalis iMX6 | Apalis iMX6D V1.0 WinEC Apalis iMX6D V1.1 WinEC Apalis iMX6Q V1.0 WinEC Apalis iMX6Q V1.1 WinEC | Not applicable |
Customer Impact: Depending on the carrier board and the amount of backfeeding, the POWER_ENABLE_MOCI might not go low enough to turn off the peripheral voltage rails in the shutdown state. Description: The POWER_ENABLE_MOCI signal is intended to be used for switching the peripheral voltage rails on the carrier board, like the 5V_SW and 3.3V_SW on the Ixora. Depending on the amount of backfeeding over the interface signals from the carrier board to the Apalis iMX6 module, the POWER_ENABLE_MOCI signal can remain between 1.0V and 1.4V in module shutdown. Depending on the carrier board circuit, this can be too high for turning off the peripheral voltage rails.
For example, on the Ixora V1.2, a different buck converter for the 5V_SW is used than on the previous versions. The threshold voltage for the enable signal is lower on the new buck converter. Depending on the backfeeding level, the 5V_SW buck converter does not get disabled in the shutdown state. The Ixora V1.0 and V1.1 are not affected by this issue since they have been using a different buck converter with a higher threshold. Workaround: Add a circuit to the carrier board for increasing the POWER_ENABLE_MOCI threshold voltage to between 2.0V and 2.5V. This could be achieved by adding a comparator or similar circuit. Such a solution is implemented in the V1.3 revision of the Ixora.
A simple voltage divider added to the POWER_ENABLE_MOCI signal can shift the voltage levels. Important: make sure that the minimum input voltage for enabling the buck converter is still guaranteed. With the AOZ2260 buck converter (which is used on Ixora V1.2), a 10k/10k voltage divider can be a suitable option. For patching such a divider, replace R15 with a 10k 0603 resistor and add another 10k resistor from the PMIC_EN_5V signal to the ground. |